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Digital - Frontend & Backend

Design Specification to Netlist and Netlist to GDSII for ASIC Development

FPGA

Micro-architecture design
ASIC / IP Prototyping and Validation with FPGA

Analog, Mixed Signal & Technology Foundation

Circuit, Layout & Char for AMS, IOs, Memories, and Std Cell Libs

Automation, AI & ML

Automation using SHELL, TCL, PERL, PYTHON, SKILL & more.

Embedded Systems

Embedded Firmware Dev, Board Bring-Up, and Validation

Client's Testimonials

Digital Frontend

Microarchitecture , RTL Design ,
RTL Sign off , Synthesis

Digital Backend

DFT, P&R, CTS, STA, PV instead of PNR,
STA Low Power implementation

Analog, Mixed Signal & Technology Foundation

Circuit, Layout & Characterization for
AMS, RF, IOs,
Memories & Std Cell Libs

Embedded
Systems

Embedded Firmware Dev
Board Bring-Up, and Validation

Automation,
AI & ML

Automation using SHELL, TCL, PERL
PYTHON, SKILL & more

FPGA

Micro-architecture design
ASIC / IP Prototyping and Validation with FPGA

Additional

Extra Service

Maintenance

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Mail Service

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Branding

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Advertise

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Cloud Server

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Brochure

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Payment

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SEO

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Digital - Frontend & Backend

Digital Design & Architecture

Micro-Architecture
RTL Design
RTL QC check : Lint, CDC etc…
SoC/Subsystem Integration
Low power design Implementation
UPF, CLP
Timing constraints, Synthesis, STA, LEC
Specialized In
- Gigabit Ethernet
- USB 3/2
- AMBA Protocols – CHI, AXI, AHB, APB
- MLM Bus Matrix – For System Bus Arbitration
Processor Architecture
- RISC-V, ARM Cortex A15, A7, ML – DLA Engine
- Interrupt Controller, Program Control, Debug, CSR, Trace Unit, MPU (Memory Protection Unit)
High-Speed SERDES
- SATA, PCIe 1-3
IP Peripherals
- UART, GPIO Controller, AES, CORDIC and Other DSP Accelerators, I2C, I2S

Digital Verification:

Advanced IP & SoC Verification
SV-UVM based Constraint – Random Verification
Test Plan, Test Bench Development, Development of BFMs, Monitors, Assertions, Checkers, Debug Automation
Low Power Verification (CPF/UPF flows)
Gate Level Simulations – Test Bench BringUp (Identification of Sync Flops, Prioritisation of TestCases, Identification of Various CDC Paths, Resolution / Upgradation of Test Failures Due to X Propagation)
PCIe, Ethernet, AMBA Protocols, RISC-V, DSP, Crypto processor – IP and Functional Verification in SoC environment
Coverage – Toggle, Code, Functional
Formal Verification
VIP Development and Integration

Post Validation Support

Post Silicon Validation – ATP and Timeset Generation for J750 and Advance Teradyne Testers
EVCD Generation for Characterization
Die Yield Analysis on wafer sort
Parameterisation Tests – IO Leakage – Analog and Digital TX / RX, Stuck at Patterns, Sequences to detect PVT Corner values for IO Calibration, Regulator Calibrations, DC IO — Measurements (GPIOs, DDR PADs for Impedance and Hysteresis) etc

DFT – Design for Testability

DFT Implementation – Scan Insertion, LBIST insertion, Test Pin-Muxing
Logic Insertion, Boundary Scan insertion, Memory BIST Insertion and IOs
ATPG, ATPG Verification
Test pattern generation and Simulation
Test mode timing constraints
Coverage Improvement

Physical Design

Block/SoC level full ownership of RTL to GDSII
Analog block integration
Low power methodology
Synthesis
STA
Floorplanning
Placement and Routing
Power planning/Optimization
Clock Tree Synthesis
Cross talk/Thermal/Noise Analysis
IR drop and Signal Integrity closure
Physical Verification (DRC,LVS,ERC,Customer Specific Checks)
ICC2, Innovus, Caliber, RC, DC, RedHawk, PT/PTSI
TCL,Shell,Perl & Python Scripting
7nm & Lower nodes | UMC, TSMC, Intel
Logical Equivalence Check

Static Timing Analysis (STA)

Setting up the STA flow
Develop timing constraints and exceptions
Timing Analysis for multi modes & multi corners
Timing ECOs using TSO or manual for timing-critical paths.

Physical Design & Verification

Setting up the Physical Design Flow
Floor Planning at Top Level & Block Level
Power Planning at Top Level & Block Level
Placement and optimization
Clock Tree Synthesis (CTS)
Routing and optimization.

Logic Equivalence Check (LEC)

Setting up the LEC flow for both functional and CLP
Develop constraints
Analysis & Debug.

Sign Off

Power Integrity (Power EM and IR-Drop)
Signal Integrity (Sig EM, IR-Drop and Noise)
Physical Verification (DRC, LVS, ERC, Customer Specific Checks)

Analog, Mixed Signal & Technology Foundation

process

What to expect! Work With Us.

Analog, Mixed Signal and RF
Memory
Standard Cell Library

Analog, Mixed Signal & Technology Foundation

We have a strong team of experts in Analog, Mixed Signal and Technology Foundation-IPs.
We have successfully delivered turnkey projects in Analog (Op-Amps, Charge-pumps etc.), Mixed Signal (DDR-IO, ADC, DAC, PLLs etc.), Memories and Std Cell Libraries for various customers.
We have expertise working with multiple fabs like TSMC, Samsung, Intel, GF, UMC etc and various technology nodes ranging from 350 nm Bi-CMOS to 5nm FINFETs

Analog, Mixed Signal and RF – Design, Verification & Layout

Analog Circuit Design
Analog Design Verification – Simulation based
Analog and Mixed Signal Modeling (AMS-Modeling)
Analog and Mixed Signal Verification (AMS-Verification)
Analog and Digital Co-Simulation
Layout Design – Analog, Mixed Signal, RF, Custom-Digital etc.
Post Layout – Extraction, Simulation and Layout/Circuit fixes.
Physical Verification (DRC, LVS, ERC, Latch-up, Soft-Conn, DFM etc.)

Memory – Design, Characterization, Validation and Layout for all below types

SRAM – Memory Instances
SRAM – Memory Compilers
Cache Memories.

Standard Cell Library – Design, Layout, Char, Lib-QC, LEF, Tech-LEF and PD-Validation for

High Performance Libraries – Multi-VT, Multi-Channel (10-Track Libs and above)
High Density Libraries – Multi-VT, Multi-Channel (8 and 9 Track Libs)
Ultra High Density Libraries – Multi-VT, Multi-Channel (6, 7 and 7.5 -Track Libs)

Embedded System Design Services

process

What to expect Work With Us.

Analog, Mixed Signal and RF
Memory
Standard Cell Library

We provide Embedded software/firmware development and porting services for Industrial Automation, Smart home automation, Computer Vision, Remote sensor networks.

Our key areas of Focus are

Product Engineering and Prototype
Hardware Design and Development
FPGA Design and Prototype
Software and Firmware Development
Digital Signal Processing
Testing and QA

Our engineering team has project experience in services for

Microcontrollers
- ARM : Texas Instruments, NXP, STM32
- RISCV : ESPRESSIF, SIFIVE
Embedded system design
- Firmware Development
- RTOS
- BSP Development – Board Support Packages (BSPs) includes boot-loader, debug utilities, interrupt handlers.
- Device Driver Development for peripheral modules
  - I2C/I3C, SPI, UART/USART, WIFI
  - Porting of drivers from HAL Libraries and CMSIS Libraries for custom changes.
  - Drivers for external I/O interfaces, audio/ video interfaces, touch screen panels, storage devices and flash memory
- Power and Algorithm Optimization
- Debug Utilities
Applications
- IOT Applications :
  - Home Automation
  - Sensor Fusion Application for industries.
- Audio / Video Applications
- AI / ML Integration – Worked on frameworks like Caffe, Keras, TensorFlow etc.

FPGA

process

What to expect Work With Us.

FPGA Selection
ASIC / IP Prototyping and Validation with FPGA
FPGA-SoC design integration

FPGA Selection
Micro-architecture design
ASIC / IP Prototyping and Validation with FPGA
Embedded hardware and software support
FPGA-to-FPGA, FPGA-to-ASIC, ASIC-to-FPGA conversion
Board design and bring-up
System Integration & Validation
FPGA-SoC design integration
RTL Coding to timing & area driven PAR
Functional Verification

Automation, AI & ML

process

What to expect Work With Us.

Analog, Mixed Signal and RF
Memory
Standard Cell Library

Analog, Mixed Signal & Technology Foundation

We have expertise in developing and implementing flows and wrapper tools for design teams
Our team has experience in scripting languages – SHELL, SKILL (Cadence), CALIBRE-RULE Writing, TCL, PERL & PYTHON
We have developed:

1. Multiple productivity improvement scripts in SKILL for Layout engineers.
2. Char-QC flow for Std Cell Library teams
3. Standard Cell Library Validation – QA flows for Physical Views like Layout, LEF Abstract
4. Wrapper tool for Physical Verification flows and reporting
5. Technology Independent Calibre rule deck generation for library QC
6. AI-based approach for circuit tuning
7. AI-based approach for timing analysis and writing TSO

Our Client's Voice

"The Engineers from Frenustech played a big role during tape out of Signalchip's SoC. They were not only dedicated towards work but always ready to put in something extra each day. They had a keen sense to learn about any new block assigned to them and were always up to challenges of the physical design of complicated blocks. The Engineers were also involved during the parasitic back annotation of complex RF blocks and tried to understand the problems being faced by the Designers and came up with innovative layout architectures to address the issues."

Nikhil BG SignalChip Innovations

We have been working with FrenusTech for the past 5 years and can confidently say that they are the best in terms of commitment and quality of deliverables. They have been a constant support at all times with their team often working late nights and during the weekends as well, during project releases. Ramesh and his team have always ensured that sufficient resources are always available if any situation arises because of change in project delivery timelines. It is always a pleasure to work with his team and hope for continued collaboration in the future.

Vishnu Siliconch

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