Digital Backend

Our team consists of leading experts in DFT, Synthesis, PnR, STA, Custom SoC/GPU Clocking and Physical Verification, delivering exceptional results in every area.

We have successfully delivered projects on Multiple Soc's, ASICs, SOCs, Automotive and Consumer Electronics

We have expertise working with multiple fabs like TSMC, Samsung, Intel, GF, UMC, etc, and various technology nodes ranging up to 18A

Physical Design

Block/SoC level full ownership of RTL to GDSII
Analog Block Integration
Low Power Methodology
Synthesis
STA
Floorplanning
Placement and Routing
Power Planning / Optimization
Clock Tree Synthesis
Cross-talk / Thermal / Noise Analysis
IR drop and Signal Integrity Closure
Physical Verification (DRC, LVS, ERC, Customer-specific Checks)
ICC2, Innovus, Caliber, RC, DC, RedHawk, PT / PTSI
TCL, SHELL, Perl & Python Scripting
5nm & Lower Nodes | UMC, TSMC, Intel, GF & more
Logical Equivalence Check

STA

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Custom Clocking

SoC Level Global Clock Distribution Planning and Custom Implementation of high frequency functional clocks, DFx clocks and PLL Reference Clocks
Modelling clock uncertainty due to systematic variations, POCV, DCD, Aging, Jitter, Thermal and Voltage Gradients etc
Methodology to distribute PLL reference clock with low Jitter

DFT – Design for Testability

DFT Implementation – Scan Insertion, LBIST Insertion, Test Pin-Muxing
Logic Insertion, Boundary Scan Insertion, Memory BIST Insertion and IOs
ATPG, ATPG Verification
Test pattern generation and Simulation
Test mode timing constraints
Coverage Improvement

Static Timing Analysis (STA)

Setting up the STA flow
Develop timing constraints and exceptions
Timing Analysis for multi modes & multi corners
Timing ECOs using TSO or manual for timing-critical paths.

Physical Design & Verification

Setting up the Physical Design Flow
Floor Planning at Top Level & Block Level
Power Planning at Top Level & Block Level
Placement and optimization
Clock Tree Synthesis (CTS)
Routing and optimization.

Digital Backend

Physical Design

STA

Custom Clocking

DFT – Design for Testability

Static Timing Analysis (STA)

Physical Design & Verification

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