Technical Skills Strong knowledge of Logic Design and HDLs like Verilog, System Verilog Should be able to write efficient constraint random test cases Should be able to develop functional test cases in C/Assembly for SoC or Processor IP Verification Experience in building or maintaining a medium to complex SV/UVM environments Code/Develop UVM components like an

Technical Skills Strong knowledge of Logic Design and HDLs like Verilog, System Verilog Should be able to write efficient constraint random test cases Should be able to develop functional test cases in C/Assembly for SoC or Processor IP Verification Experience in building or maintaining a medium to complex SV/UVM environments Code/Develop UVM components like an

Technical Skills Strong knowledge of Logic Design and HDLs like Verilog, System Verilog Should be able to write efficient constraint random test cases Should be able to develop functional test cases in C/Assembly for SoC or Processor IP Verification. Experience in building or maintaining a medium to complex SV/UVM testbench environments Code/Develop UVM components like

Technical Skills 6+ years of experience of designing and verification of Memory layouts Hands-on experience with layouts of leaf cells like control, sense amplifiers, I/O Blocks, bit cell array and decoders etc for custom macros & compilers. Should have worked on 16nm / 14nm / 10nm/ 7nm/ Finfet process technologies . Hands-on experience with top-level

Technical Skills 3+ years of experience in designing and verification of Memory layouts Hands-on experience with layouts of leaf cells like control, sense amplifiers, I/O Blocks, bit cell array and decoders, etc for custom macros & compilers. Should have worked on 16nm / 14nm / 10nm/ 7nm/ Finfet process technologies . Hands-on experience with top-level

Technical Skills Relevant industry experience in the field of Physical Design Implementation. Relevant industry experience in the field of Physical Design Implementation.  Design experience in all aspects of physical Design.   Proficient in P&R, Synthesis, STA, timing closure and Physical verification. Good experience in scripting, methodology and flow development using Shell script, TCL. Perl/Python is an

Technical Skills Relevant industry experience in the field of Physical Design Implementation. Relevant industry experience in the field of Analog mixed-signal verification. Strong understanding of analog circuit concepts. Experience in developing HDL test bench using Verilog / System Verilog / VHDL /UVM Hands-on experience working on Co-Simulation using NCSIM and SPICE, SPECTRE, or similar tools.