Technical Skills: Strong knowledge of Logic Design and HDLs like Verilog, System Verilog Should be able to write efficient constraint random test cases Should be able to develop functional test cases in C/Assembly for SoC or Processor IP Verification Experience in building or maintaining a medium to complex SV/UVM environments Code/Develop UVM components like an […]

Technical Skills 10+ years of experience of designing and verification of Memory layouts Hands-on experience with layouts of leaf cells like control, sense amplifiers, I/O Blocks, bit cell array and decoders etc for custom macros & compilers. Should have worked on 16nm / 14nm / 10nm/ 7nm/ Finfet process technologies . Hands-on experience with top-level

Technical Skills Relevant industry experience in the field of Physical Design Implementation.  Design experience in all aspects of physical Design.   Proficient in P&R, Synthesis, STA, timing closure and Physical verification. Good experience in scripting, methodology and flow development using Shell script, TCL. Perl/Python is an added advantage.  Should be good at concepts like Synthesis, Low

Technical Skills Relevant industry experience in the field of Physical Design Implementation. Design experience in all aspects of physical design. Proficient in P&R, Synthesis, STA, timing closure and Physical verification. Relevant industry experience in the field of Physical Design Implementation. Design experience in all aspects of physical Design. Proficient in P&R, Synthesis, STA, timing closure

Technical Skills 13+ years of experience of designing Analog/Mixed-Signal/RF layouts Knowledge of perl/skill/shell scripting is a plus Must have hands on experience in Analog / Mixed Signal Layout design in advanced FinFET processes like 16nm, 12nm, 10nm, 7nm, 5nm, 3nm Excellent understanding of CMOS / Bi-CMOS / SOI / FinFET process Should have excellent understanding

Technical Skills Relevant industry experience in the field of Physical Design Implementation. Design experience in all aspects of physical Design. Proficient in P&R, Synthesis, STA, timing closure and Physical verification. Good experience in scripting, methodology and flow development using Shell script, TCL. Perl/Python is an added advantage.  Should be good at concepts like Synthesis, Low

Technical Skills Relevant industry experience in the field of RTL designs. Proficient with digital logic design. Experience in IP design or SOC integration Expert in developing or integrating RTL using System verilog / Verilog / VHDL. Prior experience using industry-standard tools for Lint, CDC etc is desired. Exposure to synthesis and timing is an added