Technical Skills

• Strong knowledge of Logic Design and HDLs like Verilog, System Verilog
• Should be able to write efficient constraint random test cases
• Should be able to develop functional test cases in C/Assembly for SoC or Processor IP Verification.
• Experience in building or maintaining a medium to complex SV/UVM testbench environments
• Code/Develop UVM components like an agent, driver, monitor, and scoreboard for IP Verification.
• Regression management runs and debugging RTL/TB issues.
• Good knowledge of debugging Logs and Waveforms.
• Basic knowledge of scripting languages – Perl/Python, Linux OS, Editors (GVIM)
• Flexible enough to work in a dynamic environment and multitask seamlessly.

Additional Skills:

• It is essential that the individual has good written and oral communication skills.