Technical Skills:

• Strong knowledge of Logic Design and HDLs like Verilog, System Verilog
• Should be able to write efficient constraint random test cases
• Should be able to develop functional test cases in C/Assembly for SoC or Processor IP Verification
• Experience in building or maintaining a medium to complex SV/UVM environments
• Code/Develop UVM components like an agent, driver, monitor, and scoreboard for IP Verification
• Regression management runs and debugging RTL/TB issues.
• Good knowledge on debugging Logs and Waveforms.
• Basic knowledge of scripting languages – Perl/Python, Linux OS, Editors (GVIM)
• Should have worked on Basic IP peripheral protocols such as UART, I2C, I2S, GPIO Controller
• Flexible enough to work in a dynamic environment and multitask seamlessly.
• Knowledge on Computer Architecture is an added advantage, Digital Logic Design, and parallel computing domain-like (Multi-Core, GPU, SIMD, MIMD etc) is a plus
• Candidates must be able to take ownership of IP/Block/Subsystem Verification.
• Protocol Experience: Should have experience on AMBA ( AXI, AHB) / DDR / LPDDR / PCIe / Any other SERDES is required
• Should be strong in building new Testbench Architecture, Automation and Other BringUp activities. 
• Strong analytical and problem-solving skills.

Additional Skills:

• It is essential that the individual has good written and oral communication skills and is able to demonstrate good analysis, debug and problem-solving skills, and show high levels of initiative.
• Should be able to mentor junior engineers in the team.
• Experience in working as part of a larger team and working towards project milestones and deadlines. Handle technical deliverables with a small team of engineers.