Technical Skills

• Relevant industry experience in the field of Physical Design Implementation.
• Relevant industry experience in the field of Analog mixed-signal verification.
• Strong understanding of analog circuit concepts.
• Experience in developing HDL test bench using Verilog / System Verilog / VHDL /UVM
• Hands-on experience working on Co-Simulation using NCSIM and SPICE, SPECTRE, or similar tools.
• Expertise in scripting languages such as UNIX/LINUX Shell, and Perl/Python.
• Understanding of analog and digital signals and debugging.
• Should be Familiar with debugging in Schematic and RTL.
• Experience in Behavioral modeling or Wreal modeling using System Verilog. SVRM, Verilog AMS is an added advantage.
• Experience working on simulation tools such as Questa. AMS designer or similarly mixed-signal simulators is an added advantage.
• Should be Familiar with using Cadence Virtuoso Schematic Editor, ADE.

Additional Skills:

• It is essential that the individual has good written and oral communication skills and is able to demonstrate good analysis, debugging, and problem-solving skills, and show high levels of initiative.