Technical Skills Strong knowledge of Logic Design and HDLs like Verilog, System Verilog Should be able to write efficient constraint random test cases Should be able to develop functional test cases in C/Assembly for SoC or Processor IP Verification. Experience in building or maintaining a medium to complex SV/UVM testbench environments Code/Develop UVM components like […]

Technical Skills Relevant industry experience in the field of Physical Design Implementation. Design experience in all aspects of physical design. Relevant industry experience in the field of Analog mixed signal verification. Strong understanding of analog circuit concepts. Experience in developing HDL test bench using Verilog / System Verilog / VHDL /UVM Hands on experience working

Technical Skills Relevant industry experience in the field of DFT for IP or SOC designs. Strong in digital logic design, DFT concepts and strong analytical ability. Proficient in synthesis with DFT, scan insertion, ATPG, MBIST, JTAG. Expert in design and implementation of DFT techniques like Boundary Scan, Memory BIST, Scan Insertion & ATPG at block

Technical Skills 1+ years of experience in designing and verification of Memory layouts Hands-on experience with layouts of leaf cells like control, sense amplifiers, I/O Blocks, bit cell array and decoders etc for custom macros & compilers. Should have worked on 16nm / 14nm / 10nm/ 7nm/ Finfet process technologies . Hands-on experience with top

Technical Skills 1+ years of experience of designing Analog/Mixed-Signal/RF layouts Good exposure on FinFet layouts in lower nodes. Knowledge of perl/skill/shell scripting is a plus. Should have excellent understanding of analog layout concepts like Parasitics minimization, Matching, Shielding/isolation, Antenna effect mitigation, EM&IR, latch-up & ESD. Hands on experience in layout of Analog blocks like SERDES,

Technical Skills Relevant industry experience in the field of RTL designs. Proficient with digital logic design. Experience in IP design or SOC integration Expert in developing or integrating RTL using System verilog / Verilog / VHDL. Prior experience using industry standard tools for Lint, CDC etc is desired. Exposure to synthesis and timing is an

Technical Skills Relevant industry experience in the field of Physical Design Implementation. Design experience in all aspects of physical Design. Proficient in P&R, Synthesis, STA, timing closure and Physical verification. Good experience in scripting, methodology and flow development using Shell script, TCL. Perl/Python is an added advantage. Should be good at concepts like Synthesis, Low